1. Field of the Invention
The invention relates to a SRAM memory cell.
Memory cells of static random access memories (SRAM's) are known in which a flip-flop is used to store potential values that represent logic states. In that case, the flip-flop is made of four field-effect transistors. The memory cell also has two selection transistors, which are used for the reading in and reading out of the memory cell, and which have gates that are connected to a word line of the SRAM and connect the flip-flop to a bit line pair. Overall, then it is a six-transistor memory cell. It is also known to realize the flip-flop by using two field-effect transistors and two resistors, thereby producing a four-transistor memory cell.
2. Summary of the Invention
It is accordingly an object of the invention to provide a SRAM memory cell, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which has a small space requirement.
With the foregoing and other objects in view there is provided, in accordance with the invention, a SRAM memory cell, comprising first and second potential terminals; first and second bit lines; a bistable field-effect transistor having first and second channel terminals and a gate, the first channel terminal connected to the first potential terminal; a first resistor having one terminal connected to the second channel terminal of the bistable field-effect transistor and another terminal, remote from the one terminal, connected to the second potential terminal; a first switch element for connecting the gate of the bistable field-effect transistor to the first bit line; and a second switch element for connecting the second channel terminal of the bistable field-effect transistor to the second bit line.
In this device, a bistable field-effect transistor is used instead of a flip-flop to store two logic states. One of the logic states corresponds to the switched-off bistable transistor and the other logic state corresponds to the switched-on bistable transistor.
A bistable field-effect transistor is to be understood in this case as a transistor which bas a hysteretic current/gate voltage characteristic curve, with the result that it changes from the off state to the high-current state and vice versa only by the application of a suitable positive and a suitable negative threshold voltage. Gate voltage values between the values of the two threshold voltages do not effect a state of change. A bistable transistor can therefore be controlled, for example, by voltage pulses having a magnitude which only briefly exceeds the respective (positive or negative) threshold voltage. FIG. 2, which is explained below, illustrates a profile of the above-mentioned hysteresis function of a bistable field-effect transistor.
An article by N. Kistler, E. V. Ploeg, J. Woo and. J. Plummer entitled "Breakdown Voltage of Submicron MOSFETs in Fully Depleted SOI" in Microelectronic Manufacturing and Reliability, Volume 1802 (1992), pages 202 ff. discloses a field-effect transistor which can be used according to the invention as a bistable field-effect transistor. That reference describes a fully depleted (that is to say virtually no free charge carriers are present in its channel region in the non-conducting state) lateral n-channel field-effect transistor which is constructed by using SOI (silicon on insulator) technology. Its channel region floats, that is to say it is not connected to a fixed potential.
A substrate on which the bistable transistor is disposed is often connected to a substrate potential. It is then necessary to insulate the channel region from the substrate in order to achieve floating of the channel region. In the cited prior art, that is done by applying SOI technology. However, the bistable transistor can also be disposed vertically on a semiconductor substrate in a different manner from the cited prior art, with the result that its channel region is insulated in a simple manner from the substrate. Such a vertical bistable transistor can be produced, for example, through the use of molecular beam epitaxy. Channel lengths of a few tens of nanometers can be achieved in that way. In experiments it was ascertained that a channel length of less than 100 nm, for example 85 nm, is particularly well suited for producing a vertical bistable transistor.
It is important for the production of a bistable transistor that its channel region is depleted in the off state. In the high-current state, that is to say when a gate voltage which exceeds the positive threshold voltage is applied, a breakdown of the transistor then occurs and charge carriers are liberated by collision ionization.
At channel lengths which are greater than 1 .mu.m, it is possible to achieve sufficient depletion by using a channel region which has been contaminated a little by dopants. Shorter channel lengths permit channel regions having higher dopant concentrations. The depletion can be achieved, in particular, by widening the depletion layer of the blocked pn junction when the drain-source voltage is applied. At the short channel lengths, a sufficiently high electric field strength, which is required for the breakdown in the high-current state, is produced even at low drain-source voltages (for example &lt;3 V).
The hysteresis effect described works as follows: if the drain-source voltage of the bistable field-effect transistor is above the already mentioned minimum value, which is determined by the technology used and the dimensions of the transistor, the bistable field-effect transistor can be changed from an off state to an on or high-current state by increasing its gate-source voltage to values above a positive threshold voltage, which can likewise be set. It remains in that high-current state even when the gate-source voltage is again reduced to values below the positive threshold voltage, provided that the minimum value of the drain-source voltage is not undershot. The transistor switches off again only upon application of a sufficiently negative gate-source voltage, which falls below a negative threshold voltage. (These explanations refer to bistable transistors of the n-channel type. However, the same is correspondingly true for p-channel transistors.)
The memory cell according to the invention functions in accordance with the following principle, according to which the hysteretic behavior of the bistable field-effect transistor is utilized: in order to write in a first logic value, for example a logic one, the bistable transistor is put into its high-current state by applying a suitable gate potential (at which the positive threshold voltage of the gate-source voltage is exceeded) through the use of a first bit line. This state is maintained even when the gate-source voltage once again achieves values below the positive threshold voltage. A second logic value, for example a logic zero, is written in by changing the bistable transistor from its high-current state to the off state by applying a sufficiently negative gate-source voltage (and undershooting the negative threshold voltage). The bistable transistor can thus be controlled by voltage pulses.
The memory cell is read out by connecting the second channel terminal to a second bit line. The latter is then charged either to the value of the first potential or that of the second potential corresponding to the state of the bistable transistor.
Since a prior art flip-flop having four transistors or two transistors and two resistors is replaced according to the invention by using just a single bistable field-effect transistor and one resistor for storage, it is possible to save at least one transistor and one resistor as compared with the known solutions, as a result of which the memory cell requires less space.
If a first and a second field-effect transistor are provided in each case for writing to and reading from the memory cell, the memory cell produced with the bistable field-effect transistor is a three-transistor memory cell instead of the known six-transistor or four-transistor memory cells.
In accordance with another feature of the invention, the gate of the bistable transistor is connected through a second resistor to a third potential which ensures that it has an undefined potential at no point in time. This achieves a reduction in the susceptibility to errors for the memory cell.
In accordance with a further feature of the invention, the second bit line can be precharged to the value of a second potential at the second potential terminal prior to a reading operation.
In accordance with an added feature of the invention, the first bit line has either of two potentials of different polarity during a writing operation.
In accordance with an additional feature of the invention, the two potentials of different polarity have the same magnitude as a first potential at the first potential terminal.
In accordance with yet another feature of the invention, there is provided a first word line, the first switch element being a first field-effect transistor having a gate connected to the first word line.
In accordance with yet a further feature of the invention, there is provided a second word line, the second switch element being a second field-effect transistor having a gate connected to the second word line.
In accordance with yet an added feature of the invention, the first word line coincides with the second word line.
In accordance with a concomitant feature of the invention, the first bit line coincides with the second bit line, in other words only one bit line is present. Both the writing to and the reading from the memory cell then take place through this line. The memory cell according to the invention can therefore have either two bit lines and a single word line for controlling the first and the second transistor or just a single bit line and a respective word line for controlling the first and the second transistor. Of course, it is also possible for two bit lines and two word lines to be present in each case.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a SRAM memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.